1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit used in various types of electronic apparatuses, for example, in communication apparatuses, such as a television receiver and a mobile phone, for receiving or transmitting information, or in read/write apparatuses, such as an optical disk apparatus. The present invention also relates to an electronic apparatus, such as a read/write apparatus, including the phase-locked loop (PLL) circuit.
2. Description of the Related Art
In general, phase-locked loop (PLL) circuits are installed in various types of electronic apparatuses, such as a communication apparatus, a transmitting-and-receiving apparatus, and an optical disk apparatus, for producing an oscillation signal with high spectrum precision or for generating a frequency-locked and phase-locked clock signal for a data signal. Examples of apparatuses including the PLL circuits include a wireless communication apparatus, such as a mobile phone, a serial communication system using various cables, and a digital data recovery system (read channel) for recovery digital data written on a disk medium.
FIG. 11A is a circuit block diagram of a common phase-locked loop circuit 100Z. As shown in FIG. 11A, the phase-locked loop circuit 100Z includes an oscillating unit 101 provided with a frequency divider 102. The oscillating unit 101 generates an output oscillation signal Vout with an oscillation frequency fosci on the basis of an oscillation control signal CN (oscillation control current Icnt in this example). The frequency divider 102 divides the oscillation frequency fosci of the output oscillation signal Vout into 1/α to generate a frequency-divided oscillation signal Vout1. In this example, the oscillating unit 101 includes a current controlled oscillator (CCO) circuit 101B. However, the oscillating unit 101 may also include a voltage controlled oscillator (VCO) circuit.
The phase-locked loop circuit 100Z also includes a phase comparator 103, a current-output loop-filter driver 104 including a charge pump circuit, and a loop filter unit 106. The phase comparator 103 compares an input signal Vin with the output oscillation signal Vout from the oscillating unit 101 or the frequency-divided oscillation signal Vout1 from the frequency divider 102, and outputs a comparison result signal Comp which represents a phase difference as a result of the comparison. The phase-locked loop circuit including the loop-filter driver 104 which includes the charge pump circuit will hereinafter be referred to as a charge-pump PLL.
The loop-filter driver 104 receives the comparison result signal Comp from the phase comparator 103 and outputs a pulsed charge-pump current Icp which corresponds to the comparison result signal Comp. The loop filter unit 106 includes at least a capacitor element 164 (loop filter capacitor) with a capacitance C. The loop filter unit 106 generates the oscillation control signal CN for controlling the oscillation frequency fosci of the oscillating unit 101 using a charge voltage Vcp of the capacitor element 164 based on the charge-pump current Icp from the loop-filter driver 104. In this example, the loop filter unit 106 includes a resistor element (loop filter resistor) with a resistance R in addition to the capacitor element 164.
In the phase-locked loop circuit 100Z having the above-described structure, the input signal Vin and the output oscillation signal Vout from the oscillating unit 101 (or the frequency-divided oscillation signal Vout1 from the frequency divider 102) are input to the phase comparator 103, and the phase comparator 103 outputs the comparison result signal Comp which represents a phase error. The oscillating unit 101 is oscillated by means of the charge-pump PLL on the basis of the comparison result signal Comp. Thus, the phase of the output oscillation signal Vout is locked to that of the input signal Vin.
The phase-locked loop circuit preferably has good jitter performance and a short lock time. These factors can be optimized by adequately setting a natural frequency ωn and a damping factor ζ of the phase-locked loop circuit to suitable values. A linearized closed-loop transfer function is generally used for the analysis of the charge-pump PLL. The natural frequency ωn and the damping factor ζ can be expressed as Equations (1-1) and (1-2) (Expression (1)) given below using a circuit gain of the loop-filter driver 104 (hereinafter referred to as CP circuit gain Kcp), an input-signal/oscillation-frequency conversion gain Kosci of the oscillating unit 101 (i.e., oscillation gain, which is a VCO circuit gain Kvco in Expression (1)), the resistance R of the resistor element, and the capacitance C of the capacitor element 164.
                                                                                          ω                  n                                =                                                                                                    K                        CP                                            ⁢                                              K                        VCO                                                              C                                                                                                      (                                  1                  ⁢                                      -                                    ⁢                  1                                )                                                                                        ζ                =                                                      RC                    2                                    ⁢                                      ω                    n                                                                                                      (                                  1                  ⁢                                      -                                    ⁢                  2                                )                                                    }                            (        1        )            
In the case where the phase-locked loop circuit 100Z having the above-described structure is used, if the input signal frequency or the data rate varies, the natural frequency ωn is preferably varied in accordance with the input frequency while the damping factor ζ is maintained constant. For example, in a data recovery system for recovery data recorded on a disc medium, the data rate varies by a factor of about 2 between an inner periphery and an outer periphery of the disc. Therefore, the natural frequency ωn is preferably varied in accordance with the data rate. According to Equation (1-1), the natural frequency ωn can be varied by controlling the CP circuit gain Kcp, the VCO circuit gain Kvco, and the capacitance C. At the same time, according to Equation (1-2), the damping factor ζ can be maintained constant by varying the capacitance C and the resistance R.
In the case where the phase-locked loop circuit 100Z is manufactured as an integrated circuit (IC), a chip area for the capacitor element 164 is generally larger than that for the resistor element. Therefore, when the PLL circuit is manufactured as an IC, it is economically disadvantageous to provide many capacitor elements to make the capacitance C variable. If the capacitance C is not variable, the resistance R is the only independent variable for the natural frequency ωn and the damping factor ζ.
In view of the above situation, the capacitance C may be set constant and a plurality of resistor elements may be provided in a switchable manner so that the resistance R can be set to various values. However, in the structure including a plurality of resistor elements which can be switched by respective switches, in the case where it is necessary to switch a time constant C·R of the loop filter unit 106 in multiple steps, a large number of resistor elements are arranged together with respective switches and are subjected to switching control. Therefore, the number of resistor elements is limited and it is difficult to perform fine adjustment. As a result, it may be difficult to form the phase-locked loop circuit as an IC depending on the use thereof.
Accordingly, there has been a demand for a PLL circuit which can be formed as an IC irrespective of the use thereof. To comply with such a demand, a structure described in, for example, Japanese Unexamined Patent Application Publication No. 10-84279 (hereinafter referred to as Patent Document 1), has been proposed.
FIG. 11B shows a phase-locked loop circuit disclosed in Patent Document 1. In the structure described in Patent Document 1, a loop filter is composed of an integration circuit (only a capacitor element (capacitor 15) is provided in FIG. 1 of Patent Document 1), and a voltage-current conversion circuit (gm amplifier 16) which converts a voltage generated by the integration circuit into a current is provided. A first charge pump (charge pump circuit 13) is provided to drive the integration circuit, and a second charge pump (charge pump circuit 14) is additionally provided. In addition, an adding unit (adder 17) for adding a current from the second charge pump and a current from the voltage-current conversion circuit is also provided. With this structure, a circuit equivalent to a CR loop filter can be formed and a phase-locked loop circuit which can be easily formed as an IC can be obtained.
The natural frequency ωn and the damping factor ζ of the phase-locked loop circuit described in Patent Document 1 can be expressed as Equations (2-1) and (2-2) (Expression (2)) given below using a circuit gain (hereinafter referred to as a CPC circuit gain Kcpc) of the first charge pump for driving the integration circuit, a circuit gain (hereinafter referred to as a CPR circuit gain Kcpr) of the second charge pump, and a gain gm of the voltage-current conversion circuit.
                                                                                          ω                  n                                =                                                                                                    K                        CPC                                            ⁢                                              g                        m                                            ⁢                                              K                        CCO                                                              C                                                                                                      (                                  2                  ⁢                                      -                                    ⁢                  1                                )                                                                                        ζ                =                                                                            CK                      CPR                                                              2                      ⁢                                              g                        m                                            ⁢                                              K                        CPC                                                                              ⁢                                      ω                    n                                                                                                      (                                  2                  ⁢                                      -                                    ⁢                  2                                )                                                    }                            (        2        )            
As is clear from Expression (2), the natural frequency ωn and the damping factor ζ can be varied without changing the capacitance C or the resistance R by varying the circuit gains (CPC circuit gain Kcpc and CPR circuit gain Kcpr) of the two charge pumps and the gain gm of the voltage-current conversion circuit. Thus, the natural frequency ωn can be varied while, for example, the damping factor ζ is maintained constant, as described above.
As is clear from the comparison between Expressions (1) and (2), the resistance R in Expression (1) corresponds to (CPR circuit gain Kcpr)/(gm·(CPC circuit gain Kcpc)). These gains can be easily varied.
However, when the phase-locked loop circuit is manufactured as an IC in practice, the parameters which determine the natural frequency ωn and the damping factor ζ, that is, the parameters such as the charge-pump current, the gain gm, and the input-signal/oscillation-frequency conversion gain Kosci, may differ from the design values. Therefore, it is difficult to set the natural frequency ωn and the damping factor ζ to desired values. In addition, the phase-locked loop circuit is generally used in various environments, and the above-mentioned parameters also vary in accordance with the temperature. Therefore, the natural frequency ωn and the damping factor ζ may become shifted from the set values.
If the natural frequency ωn largely differs from the set value thereof, a time for the phase of the output oscillation signal Vout to be locked to that of the input signal Vin, that is, an acquisition time, also differs from the set value. Therefore, it becomes difficult to design the overall system including the phase-locked loop circuit. In addition, if the natural frequency ωn becomes lower than the desired value, the jitter increases. To avoid such a problem, there has been a demand for a technique to compensate for the manufacturing variations and the temperature characteristics of the input-signal/oscillation-frequency conversion gain Kosci.
To comply with such a demand, structures described in the following documents have been proposed:
Takashi Morie, Shiro Dosho, Kouji Okamoto, Yuji Yamada and Kazuaki Sogawa, “A-90dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit”, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp. 52-55 (hereinafter referred to as Non-Patent Document 1); and
Takeo Yasuda, “HIGH-SPEED WIDE-LOCKING RANGE VCO WITH FREQUENCY CALIBRATION”, IEEE Int. Symp. On Circuits and Systems, May 28-31, 2000, pp. III45-III48 (hereinafter referred to as Non-Patent Document 2).
FIG. 11C shows the structure according to Non-Patent Document 1. The structure according to Non-Patent Document 1 includes a high-precision bias circuit which is not affected by a temperature variation and which serves to maintain the charge-pump current constant. In addition, a gain control amplifier which adjusts the gain for an oscillation control signal CN is provided on the input side of a voltage controlled oscillator (VCO). The gain of the voltage controlled oscillator (VCO) is measured, and the gain control amplifier is controlled on the basis of a correction value which corresponds to the result of the measurement. Thus, a feedback signal is input to the voltage controlled oscillator (VCO).
In the structure according to Non-Patent Document 1, each gain is calibrated before the operation as a PLL is started. First, to calibrate the gain of the voltage controlled oscillator VCO, reference voltages Vrefs shown in FIG. 11C are supplied to the voltage controlled oscillator VCO to oscillate the voltage controlled oscillator VCO. Two voltages Vrefs, which are 2 V and 1 V, are prepared in this example and an oscillation frequency is determined for each of the voltages by a gain controller GainCnt. The VCO gain is the difference between the oscillation frequencies, and magnitude relationship between the thus-determined VCO gain and a target VCO gain is determined. The result of the determination is fed back to a voltage-current (VI) conversion circuit. The above-described process is repeated N times. Thus, the gain of the VI conversion circuit is digitally changed so as to calibrate the VCO gain. In addition, a current having information regarding a temperature dependency compensation using a dummy filter circuit and a diode is used as a bias current of a charge pump CP1. Thus, variation in ωn due to the filter and the temperature variation is calibrated.
FIGS. 11D and 11E show the structure according to Non-Patent Document 2. FIG. 11D shows the overall structure, and FIG. 11E shows the structure of a single delay cell of a VCO included in the overall structure. In the structure according to Non-Patent Document 2, a control voltage is clamped between an upper limit and a lower limit by a clamping circuit CLP, and an oscillating frequency range is calibrated within a voltage range between the upper and lower limits. The PLL is caused to lock at upper-limit and lower-limit frequencies using Ref.Clock and frequency dividers “DIVIDE by D” and “DIVIDE by N”, and the magnitude relationship between the voltages corresponding to the oscillations at the locked frequencies is determined by a comparator CMP. Then, a switch transistor connected to a current-source transistor shown in FIG. 11E is digitally controlled such that the voltages corresponding to the upper-limit and lower-limit frequencies are within the clamping voltage range. As a result, a desired oscillation frequency can be obtained within a predetermined voltage dynamic range.